VLSI Implementation of a 4×4-bit Multiplier in a Two Phase Drive Adiabatic Dynamic CMOS Logic(<Special Section>VLSI Technology toward Frontiers of New Market)
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概要
- 論文の詳細を見る
An adiabatic logic is a technique to design low power digital VLSI's. This paper describes the design and VLSI implementation of a multiplier using a two phase drive adiabatic dynamic CMOS logic (2PADCL) circuit. Circuit operation and performance have been evaluated using a 4×4-bit 2PADCL multiplier fabricated in a 1.2μm CMOS process. The experimental results show that the multiplier was operated with clock frequencies 800kHz. The total power dissipation of the 4×4-bit 2PADCL multiplier was also 5.19mW at the 1.5V DC power supply voltage.
- 社団法人電子情報通信学会の論文
- 2007-10-01
著者
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Takahashi Yasuhiro
Department of Internal Medicine (Division of Cardiology, Hepatology, Geriatrics and Integrated Medic
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Sekine Toshikazu
Department Of Electrical And Electronic Engineering Faculty Of Engineering Gifu University
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YOKOYAMA Michio
Department of Bio-system Engineering, Faculty of Engineering, Yamagata University
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Takahashi Yasuhiro
Department Of Electrical And Electronic Engineering Faculty Of Engineering Gifu University
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Yokoyama Michio
Department Of Bio-system Engineering Faculty Of Engineering Yamagata University
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Takahashi Yasuhiro
Department Of Biological Sciences Graduate School Of Science Osaka University
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