A 70MHz Multiplierless FIR Hilbert Transformer in 0.35μm Standard CMOS Library(VLSI Design Technology and CAD)
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概要
- 論文の詳細を見る
This paper presents the implementation of a 31-tap FIR Hilbert transform digital filter chip used in the digital-IF receivers, to confirm the effectiveness of our new design method. Our design method that we previously reported is based on a computation sharing multiplier using a new horizontal and vertical common subexpression techniques. A 31-tap FIR Hilbert transform digital filter was implemented and fabricated in 0.35μm CMOS standard cell library. The chip's core contains approximately 33k transistors and occupies 0.86mm^2. The chip also has an operating speed of 70MHz over. The implementation results show that the proposed Hilbert transformer has a smallest cost factor and so that is a high performance filter.
- 社団法人電子情報通信学会の論文
- 2007-07-01
著者
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Takahashi Yasuhiro
Department of Internal Medicine (Division of Cardiology, Hepatology, Geriatrics and Integrated Medic
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Sekine Toshikazu
Department Of Electrical And Electronic Engineering Faculty Of Engineering Gifu University
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YOKOYAMA Michio
Department of Bio-system Engineering, Faculty of Engineering, Yamagata University
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Takahashi Yasuhiro
Department Of Electrical And Electronic Engineering Faculty Of Engineering Gifu University
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Yokoyama Michio
Department Of Bio-system Engineering Faculty Of Engineering Yamagata University
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Takahashi Yasuhiro
Department Of Biological Sciences Graduate School Of Science Osaka University
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