A clock line for a large scale reconfigurable data paths processor (超伝導エレクトロニクス)

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概要

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• Clocking of the large scale SFQ circuits is a major issue due to accumulated jitter and clock skew that grow with the increase of the clock line length. We have considered two different clocking schemes, linear and tree, for employment in the SFQ Reconfigurable Data Paths processor (SFQ-RDP). The impact of the accumulated jitter on the clock frequency has been estimated and a synchronization scheme proposed.

• 2009-10-13

著者

• Fujimaki Akira

  Department Of Quantum Engineering Nagoya University

• Fujimaki Akira

  Nagoya Univ. Nagoya‐shi Jpn

• Fujimaki Akira

  Department Of Quantum Engineering Nagoya University:crest-jst

• AKAIKE Hiroyuki

  Department of Electronics, Nagoya University

• KATAEVA Irina

  Department of Quantum Engineering, Nagoya University

• Kataeva Irina

  Department Of Quantum Engineering Nagoya University

• Akaike Hiroyuki

  Department Of Quantum Engineering Nagoya University

• Akaike Hiroyuki

  Department Of Electronics Faculty Of Engineering Nagoya University

• Akaike H

  Nagoya Univ. Nagoya Jpn

• Akaike Hiroyuki

  Nagoya Univ. Nagoya‐shi Jpn

関連論文

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