Design and Demonstration of Pipelined Circuits Using SFQ Logic(<特集>Special Issue on Superconductive Electronics)

概要

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We have designed the Half Adder (HA) circuit and the Carry Save Serial Adder (CSSA) circuit based on pipeline architecture. Our HA has the structure of a two-stage pipeline and consists of 160 Josephson Junctions (JJs). Our CSSA has the structure of a four-stage pipeline with a feedback loop and consists of 360 JJs. These circuits were fabricated by the NEC standard process. There are two issues which should be consid- ered in the design. One is parameter spreads generated by the fabrication process and the other is leakage currents between the gates. We have introduced a parameter optimization method to deal with the parameter spreads. We have also inserted three stages of JTLs to reduce leakage currents. We have experimen- tally confirmed the correct operations of these circuits. The ob- tamed bias margins were ±33.1% for the HA and ±24.6% for the CSSA.
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2002-03-01