Novel Implantation Method to Improve Machine-Model Electrostatic Discharge Robustness of Stacked N-Channel Metal-Oxide Semiconductors (NMOS) in Sub-Quarter-Micron Complementary Metal-Oxide Semiconductors (CMOS) Technology : Semiconductors
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概要
- 論文の詳細を見る
- 社団法人応用物理学会の論文
- 2002-11-15
著者
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Ker M‐d
National Chiao‐tung Univ. Hsinchu Twn
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KER Ming-Dou
Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, National Chiao-Tung Univ
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Ker Ming-dou
Nanoelectronics And Gigascale Systems Laboratory Institute Of Electronics National Chiao-tung Univer
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Peng Jeng-jie
Esd Protection Technology Department Soc Technology Center Industrial Technology Research Institute
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HSU Hsin-Chyh
Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, National Chiao-Tung Univ
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Hsu Hsin-chyh
Nanoelectronics And Gigascale Systems Laboratory Institute Of Electronics National Chiao-tung Univer
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Hsu Hsin-chyh
Nanoelectronics And Gigascale Systems Laboratory Institute Of Electronics National Chiao-tung Univer
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- Impedance-Isolation Technique for ESD Protection Design in RF Integrated Circuits
- Novel Implantation Method to Improve Machine-Model Electrostatic Discharge Robustness of Stacked N-Channel Metal-Oxide Semiconductors (NMOS) in Sub-Quarter-Micron Complementary Metal-Oxide Semiconductors (CMOS) Technology : Semiconductors
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- High-Current Characterization of Polysilicon Diode for Electrostatic Discharge Protection in Sub-Quarter-Micron Complementary Metal Oxide Semiconductor Technology
- Active Electrostatic Discharge (ESD) Device for On-Chip ESD Protection in Sub-Quarter-Micron Complementary Metal-Oxide Semiconductor (CMOS) Process