On the Complexity of Fault Testing for Reversible Circuits

概要

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This paper shows that it is NP-hard to generate a minimum complete test set for stuck-at faults on a set of wires of a reversible circuit.
一般社団法人電子情報通信学会の論文
2005-11-03

著者

Tayu Satoshi
Department Of Communication And Integrated Systems Tokyo Institute Of Technology
Ito Shigeru
Department Of Communications And Integrated Systems Tokyo Institute Of Technology
Ueno Shuichi
Department Of Biological Science Faculty Of Science Yamaguchi University
Ito Yusuke
Department Of Anesthesiology Tokyo Medical And Dental University Graduate School Of Medicine
UENO Shuichi
Department of Communications and Integrated Systems, Tokyo Institute of Technology

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On the Complexity of Fault Testing for Reversible Circuits

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