Device Simulation of a Thin-Film Silicon on Insulator Power Metal-Oxide-Semiconductor Field-Effect Transistor for Structure Optimization

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概要

• 論文の詳細を見る

• This paper proposes an optimised device structure based on the results of numerically simulating thin-film silicon on insulator (SOI) power metal-oxide-semiconductor field-effect transistors (MOSFETs) in the 50-V class. The dependence of the breakdown voltage and specific on-resistance on the doping concentration of the drain offset region, on the thickness of the superficiai silicon layer, on the thickness of the buried oxide layer, and on the drain offset length are compared for buried channel MOSFETs and surface channel MOSFETs.

• 社団法人応用物理学会の論文
• 1994-01-30

著者

• MATSUMOTO Satoshi

  NTT Intefrated Information & Energy Systems Laboratories

• Yoshino H

  Ntt Electronics Technology

• Matsumoto Satoshi

  Ntt Interdisciplinary Research Laboratories

• YOSHINO Hideo

  NTT Electronics Technology

関連論文

• Application of Reversed Silicon Wafer Direct Bonding to Thin-Film SOI Power ICs
• Application of Reversed Silicon Wafer Direct Bonding to Thin-Film SOI Power Ics
• Failure Analysis and New Design of a Thin-Film Silicon-on-Insulator Power Metal-Oxide-Semiconductor Field-Effect Transistor Based on Emission Microscopy and 2-Dimensional Device Simulation
• Switching Characteristics of a Thin Film SOI Power MOSFET
• Integration of a Power Supply for System-on-Chip (Special Section on Analog Circuit Techniques for System-on-Chip Integration)
• Hot-Carrier Effect of an Ultra-Thin-Film SOI Power MOSFET
• Study on Parasitic Bipolar Effect in a 200-V-Class Power MOSFET Using Silicon Direct Bonding SOI Wafer (Special Issue on SOI Devices and Their Process Technologies)
• Device Simulation of a Thin-Film Silicon on Insulator Power Metal-Oxide-Semiconductor Field-Effect Transistor for Structure Optimization
• Effect of Buried Oxide Thickness in a Thin-Film Silicon on Insulator Power Metal-Oxide-Semiconductor Field-Effect Transistor

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