1Gbit DDR SDRAM for Low Voltage and High Speed Application (Invited)
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概要
- 論文の詳細を見る
A double data rate at 333Mb/s/pin is achieved for a 2.5V 1Gb synchronous DRAM in a 0.14μm process. The large density of integration and severe device fluctuation present challenges in dealing with the on-chip skews, packaging and processing technology. Circuit techniques and schemes of ODIC chip with non-ODIC package, cycle-time adaptive wave pipelining, and variable stage analog DLL with the three-input phase detector can provide precise skew controls and increased tolerance to processing variations. Double data rate as a viable high-speed and low-voltage DRAM I/O interface is demonstrated.
- 社団法人電子情報通信学会の論文
- 1999-07-23
著者
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Cho Soo
Memory Product And Technology Division Samsung Electronics
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Kim Nam
Memory Research and Development Division, Hyundai Electronics Industries Co., Ltd.
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Kim Nam
Memory Product And Technology Division Samsung Electronics
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Byun Sang
Memory Product And Technology Division Samsung Electronics
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Lee Jae
Memory Product And Technology Division Samsung Electronics
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Yoon Hongil
Memory Product and Technology Division, Samsung Electronics
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Kim Keum
Memory Product and Technology Division, Samsung Electronics
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Rhee Sang
Memory Product and Technology Division, Samsung Electronics
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Lee Hyun
Memory Product and Technology Division, Samsung Electronics
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Ko Tae
Memory Product and Technology Division, Samsung Electronics
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Ko Tae
Memory Product And Technology Division Samsung Electronics
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Lee Hyun
Memory Product And Technology Division Samsung Electronics
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Rhee Sang
Memory Product And Technology Division Samsung Electronics
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Kim Keum
Memory Product And Technology Division Samsung Electronics
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Yoon Hongil
Memory Product And Technology Division Samsung Electronics
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- 1Gbit DDR SDRAM for Low Voltage and High Speed Application (Invited)
- 1Gbit DDR SDRAM for Low Voltage and High Speed Application (Invited)
- 1Gbit DDR SDRAM for Low Voltage and High Speed Application (Invited)
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