High-Voltage MOS Devices with High Energy Implanted Buried Layer : Low-Voltage CMOS Process Comparable High-Voltage MOS Devices(AWAD2003 : Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices)

概要

論文の詳細を見る
We implemented 25V bi-directional MOS devices in a 0.35μm standard low-voltage CMOS process. These devices have high breakdown voltage by using high energy implanted buried layer. To obtain farther improvement in the performance of the devices, self-aligned process is used for forming drift regions. And to decrease the product cost of high voltage integrated circuit (HVIC), high voltage well is not defined separately from low voltage well. In this paper, we present the process integration and the high-voltage device performance of 25V HVIC processes. We obtained the specific on-resistances of 0.64mΩ・cm^2 and 1.35mΩ・cm^2 for n-channel and p-channel 25V bi-directional devices, respectively. The breakdown voltage of developed devices is more than 28V.
社団法人電子情報通信学会の論文
2003-06-23