Low Supply Voltage and Low-Power 1-GHz PLL Frequency Synthesizer for Mobile Terminals(Regular Section)
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概要
- 論文の詳細を見る
We introduce a PLL (Phase Locked Loop) for low-power and a low supply voltage applications. Because the PLL is a key device of the system LSIs used in mobile terminals, it is very important that PLLs operate under a low supply voltage to reduce power consumption. We investigate the limitations of the conventional VCO that uses common load transistors. Furthermore, we propose a charge pump that uses a dynamic output stage opamp and a stability technique for the CMOS process, and it does not contain any special resistors. The results of an evaluation of a device fabricated using a standard logic 0.18-μm CMOS process demonstrated that the proposed PLL operated above 1.0 GHz with a 1.2-V supply voltage and it produced only a small amount of jitter that was lower than 78 ps_p-p.
- 2003-01-01
著者
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KOKUBO Masaru
Central Research Laboratory, Hitachi, Ltd.
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SHIBAHARA Yoshiyuki
Central Research Laboratory, Hitachi Ltd.
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AOKI Hirokazu
Semiconductor and Integrated Circuits group, Hitachi Ltd.
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HWANG Changku
MIPS Processor Division, PMC-Sierra Inc.
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Kokubo M
Communication Device Research Department Central Research Laboratory Hitachi Ltd.
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Kokubo Masaru
Central Research Laboratory Hitachi Ltd.
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Kokubo Masaru
Communication Device Research Department Central Research Laboratory Hitachi Ltd.
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Hwang C
Micrys Inc.:(present Address) Research & Development Division Hitachi America Ltd.
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Hwang Changku
Mips Processor Division Pmc-sierra Inc.
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Aoki H
Modech Inc. Hachioji-shi Jpn
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Aoki H
Toshiba Corp. Yokohama‐shi Jpn
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Shibahara Y
Central Research Laboratory Hitachi Ltd.
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Shibahara Yoshiyuki
Central Research Laboratory Hitachi Ltd.
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