A 0.7-V 200-MHz Self-Calibration PLL(Special Issue on High-Performance Analog Integrated Circuits)

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概要

• 論文の詳細を見る

• Problems concerning a phase-locked loop (PLL) fabricated by a deep-sub-micron process were investigated, and a high-speed self-calibration technique for tuning a voltage-controlled oscillator (VCO) frequency range automatically was developed. The self-calibration technique can measure VCO frequency in short time by comparing intervals between a PLL reference and a VCO output. Furthermore, a loop-filter bypassing method was also used to change the calibration frequency in short time. At 0.7 V and 200 MHz, the prototype PLL has a calibration time of 1.4μs and a total settling time of 10μs, which are adequate for microprocessor applications. Moreover, the PLL has a cycle-to-cycle jitter of 142ps and a power consumption of 470μW.

• 2002-08-01

著者

• KOKUBO Masaru

  Central Research Laboratory, Hitachi, Ltd.

• SHIBAHARA Yoshiyuki

  Central Research Laboratory, Hitachi Ltd.

• Kokubo Masaru

  Central Research Laboratory Hitachi Ltd.

• Shibahara Yoshiyuki

  Central Research Laboratory Hitachi Ltd.

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