Efficient Vector Compaction Methods for Power Estimation with Consecutive Sampling Techniques(VLSI Design Technology and CAD)

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概要

• 論文の詳細を見る

• For large circuits, vector compaction techniques could provide a faster solution for power estimation with reasonable accuracy. Because traditional sampling approach will incur useless transitions between every sampled pattern pairs after they are concatenated into a single sequence for simulation, we proposed a vector compaction method with grouping and single-sequence consecutive sampling technique to solve this problem. However, it is very possible that we cannot find a perfect consecutive sequence without any undesired transitions. In such cases, the compaction ratio of the sequence length may not be improved too much. In this paper, we propose an efficient approach to relax the limitation a little bit such that multiple consecutive sequences are allowed. We also propose an algorithm to reduce the number of sequences instead of setting the number as one to find better solutions for vector compaction problem. As demonstrated in the experimental results, the average compaction ratio and speedup can be significantly improved by using this new approach.

• 社団法人電子情報通信学会の論文
• 2004-11-01

著者

• Jou Jing-yang

  The Department Of Electronics Engineering National Chiao-tung University

• Liu Chien-nan

  The Department Of Electrical Engineering National Central University

• Jou J‐y

  The Department Of Electronics Engineering National Chiao-tung University

• HSU Chih-Yang

  the Department of Electronics Engineering, National Chiao-Tung University

• Jou Jing-yang

  The Department Of Electronic Engineering National Chiao-tung University

• Hsu Chih-yang

  The Department Of Electronics Engineering National Chiao-tung University

関連論文

• An Efficient Approach to Build Accurate Behavioral Models of PLL Designs( Analog Circuit Techniques and Related Topics)
• A Variable Partitioning Algorithm of BDD for FPGA Technology Mapping (Special Section on VLSI Design and CAD Algorithms)
• Efficient Vector Compaction Methods for Power Estimation with Consecutive Sampling Techniques(VLSI Design Technology and CAD)
• An Efficient Power Model for IP-Level Complex Designs (VLSI Design Technology and CAD)
• A New Method for Constructing IP Level Power Model Based on Power Sensitivity (Special Section on VLSI Design and CAD Algorithms)
• Delay-Optimal Technology Mapping for Hard-Wired Non-Homogeneous FPGAs (Special Section on VLSI Design and CAD Algorithms)

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