Jou Jing-yang | The Department Of Electronic Engineering National Chiao-tung University
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概要
- JOU Jing-Yangの詳細を見る
- 同名の論文著者
- The Department Of Electronic Engineering National Chiao-tung Universityの論文著者
関連著者
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Jou Jing-yang
The Department Of Electronic Engineering National Chiao-tung University
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Jou Jing-yang
The Department Of Electronics Engineering National Chiao-tung University
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Jou J‐y
The Department Of Electronics Engineering National Chiao-tung University
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Liu Chien-nan
The Department Of Electrical Engineering National Central University
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Jiang Jie-hong
The Department Of Electronics Engineering National Chiao Tung University
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Wei Jung-shian
The Department Of Electronics Engineering National Chiao Tung University
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Huang Juinn-dar
The Department Of Electronics Engineering National Chiao Tung University
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Shen Wen-zen
The Department Of Electronic Engineering National Chiao-tung University
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Huang Heng-liang
The Department Of Electronic Engineering National Chiao-tung University
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HSU Chih-Yang
the Department of Electronics Engineering, National Chiao-Tung University
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Lin Jiing-yuan
Global Unichip Corporation
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Hsu Chih-yang
The Department Of Electronics Engineering National Chiao-tung University
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CHUANG Hsien-Ho
the Department of Electronics Engineering National Chiao Tung University
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SHUNG C.Bernard
the Department of Electronics Engineering National Chiao Tung University
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Shung C
The Department Of Electronics Engineering National Chiao Tung University
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Shung C.bernard
The Department Of Electronics Engineering And Institute Of Electronics National Chiao Tung Universit
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Chuang H‐h
The Department Of Electronics Engineering National Chiao Tung University
著作論文
- A Variable Partitioning Algorithm of BDD for FPGA Technology Mapping (Special Section on VLSI Design and CAD Algorithms)
- Efficient Vector Compaction Methods for Power Estimation with Consecutive Sampling Techniques(VLSI Design Technology and CAD)
- A New Method for Constructing IP Level Power Model Based on Power Sensitivity (Special Section on VLSI Design and CAD Algorithms)
- Delay-Optimal Technology Mapping for Hard-Wired Non-Homogeneous FPGAs (Special Section on VLSI Design and CAD Algorithms)