A Variable Partitioning Algorithm of BDD for FPGA Technology Mapping (Special Section on VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• Field Programmable Gate Arrays (FPGA's) are important devices for rapid system prototyping. Roth-Karp decomposition is one of the most popular decomposition techniques for Look-Up Table (LUT)-based FPGA technology mapping. In this paper, we propose a novel algorithm based on Binary Decision Diagrams (BDD's) for selecting good lambda set variables in Roth-Karp decomposition to minimize the number of consumed configurable logic blocks (CLB's) in FPGA's. The experimental results on a set of benchmarks show that our algorithm can produce much better results than the similar works of the previous approaches [1], [4].

• 社団法人電子情報通信学会の論文
• 1997-10-25

著者

• Jou Jing-yang

  The Department Of Electronics Engineering National Chiao-tung University

• Jiang Jie-hong

  The Department Of Electronics Engineering National Chiao Tung University

• Wei Jung-shian

  The Department Of Electronics Engineering National Chiao Tung University

• Jou J‐y

  The Department Of Electronics Engineering National Chiao-tung University

• Huang Juinn-dar

  The Department Of Electronics Engineering National Chiao Tung University

• Jou Jing-yang

  The Department Of Electronic Engineering National Chiao-tung University

関連論文

• A Variable Partitioning Algorithm of BDD for FPGA Technology Mapping (Special Section on VLSI Design and CAD Algorithms)
• Efficient Vector Compaction Methods for Power Estimation with Consecutive Sampling Techniques(VLSI Design Technology and CAD)
• An Efficient Power Model for IP-Level Complex Designs (VLSI Design Technology and CAD)
• A New Method for Constructing IP Level Power Model Based on Power Sensitivity (Special Section on VLSI Design and CAD Algorithms)
• Delay-Optimal Technology Mapping for Hard-Wired Non-Homogeneous FPGAs (Special Section on VLSI Design and CAD Algorithms)

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