Jou Jing-yang | The Department Of Electronics Engineering National Chiao-tung University

スポンサーリンク

概要

• 同名の論文著者
• The Department Of Electronics Engineering National Chiao-tung Universityの論文著者

関連著者

• Jou Jing-yang

  The Department Of Electronics Engineering National Chiao-tung University

• Jou J‐y

  The Department Of Electronics Engineering National Chiao-tung University

• Jou Jing-yang

  The Department Of Electronic Engineering National Chiao-tung University

• Liu Chien-nan

  The Department Of Electrical Engineering National Central University

• HSU Chih-Yang

  the Department of Electronics Engineering, National Chiao-Tung University

• Hsu Chih-yang

  The Department Of Electronics Engineering National Chiao-tung University

• Liu Chien-nan

  Department Of Electrical Electioneering National Central University

• Jiang Jie-hong

  The Department Of Electronics Engineering National Chiao Tung University

• Wei Jung-shian

  The Department Of Electronics Engineering National Chiao Tung University

• Huang Juinn-dar

  The Department Of Electronics Engineering National Chiao Tung University

• HSU Chih-Yang

  Department of Electronics Engineering, National Chiao-Tung University

• JOU Jing-Yang

  Department of Electronics Engineering, National Chiao-Tung University

• Jou Jing-yang

  Department Of Electronics Engineering National Chiao Tung University

• CHUANG Hsien-Ho

  the Department of Electronics Engineering National Chiao Tung University

• SHUNG C.Bernard

  the Department of Electronics Engineering National Chiao Tung University

• Shung C

  The Department Of Electronics Engineering National Chiao Tung University

• Shung C.bernard

  The Department Of Electronics Engineering And Institute Of Electronics National Chiao Tung Universit

• Chuang H‐h

  The Department Of Electronics Engineering National Chiao Tung University

• Jou Jing-yang

  Department Of Electronics Engineering And Institute Of Electronics National Chiao Tung University

もっと見る 閉じる

著作論文

• A Variable Partitioning Algorithm of BDD for FPGA Technology Mapping (Special Section on VLSI Design and CAD Algorithms)
• Efficient Vector Compaction Methods for Power Estimation with Consecutive Sampling Techniques(VLSI Design Technology and CAD)
• An Efficient Power Model for IP-Level Complex Designs (VLSI Design Technology and CAD)
• Delay-Optimal Technology Mapping for Hard-Wired Non-Homogeneous FPGAs (Special Section on VLSI Design and CAD Algorithms)

スポンサーリンク