Delay-Optimal Technology Mapping for Hard-Wired Non-Homogeneous FPGAs (Special Section on VLSI Design and CAD Algorithms)

スポンサーリンク

概要

• 論文の詳細を見る

• A delay-optimal technology mapping algorithm is developed on a general model of FPGA with hard-wired non-homogeneous logic block architectures which is composed of different sizes of look-up tables(LUTs) hard-wired together. This architecture has the advantages of short delay of hard-wired connections and area-efficiency of non-homogeneous structure. The Xilinx XC4000 is one commercial example, where two 4-LUTs are hard-wired to one 3-LUT. In this paper, we present a two-dimensional labeling approach and a level-2 node cut algorithm to handle the hard-wired feature. The experimental results show that our algorithm generates favorable results for Xilinx XC4000 CLBs. Over a set of MCNC benchmarks, our algorithm produces results with 17% fewer CLB depth than that of FlowMap in similar CPU time on average, and with 4% fewer CLB depth than that of PDDMAP on average while PDDMAP needs 15 times more CPU time.

• 社団法人電子情報通信学会の論文
• 2000-12-25

著者

• Jou Jing-yang

  The Department Of Electronics Engineering National Chiao-tung University

• Jou Jing-yang

  The Department Of Electronic Engineering National Chiao-tung University

• CHUANG Hsien-Ho

  the Department of Electronics Engineering National Chiao Tung University

• SHUNG C.Bernard

  the Department of Electronics Engineering National Chiao Tung University

• Shung C

  The Department Of Electronics Engineering National Chiao Tung University

• Shung C.bernard

  The Department Of Electronics Engineering And Institute Of Electronics National Chiao Tung Universit

• Chuang H‐h

  The Department Of Electronics Engineering National Chiao Tung University

関連論文

• A Variable Partitioning Algorithm of BDD for FPGA Technology Mapping (Special Section on VLSI Design and CAD Algorithms)
• Efficient Vector Compaction Methods for Power Estimation with Consecutive Sampling Techniques(VLSI Design Technology and CAD)
• An Efficient Power Model for IP-Level Complex Designs (VLSI Design Technology and CAD)
• A New Method for Constructing IP Level Power Model Based on Power Sensitivity (Special Section on VLSI Design and CAD Algorithms)
• Delay-Optimal Technology Mapping for Hard-Wired Non-Homogeneous FPGAs (Special Section on VLSI Design and CAD Algorithms)
• An Efficient Architecture for Multicasting in Shared Buffer ATM Switches

スポンサーリンク