A New Method for Constructing IP Level Power Model Based on Power Sensitivity (Special Section on VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• As the function of a system getting more complex, IP(Intellectual Property) reusing is the trend of system design style. Designers need to evaluate the performance and features of every candidate IP block that can be used in their design, while IP providers hope to keep the structure of their IP blocks a secret. An IP level power model is a model that takes only the primary input statistics as parameters and does not reveal any information about the sizes of the transistors or the structure of the circuit. This paper proposes a new method for constructing power model that is suitable for IP level circuit blocks. It is a nominal point selection method for power models based on power sensitivities. By analyzing the relationship between the dynamic power consumption of CMOS circuits and their input signal statistics, a guideline of selecting the nominal point is proposed. From our analysis, the first nominal point is selected to minimize the average estimation error and two other nominal points are selected to minimize the maximum estimation error. Our experimental results on a number of benchmark circuits show the effectiveness of the proposed method. Average estimation accuracy within 5.78% of transistor level simulations is achieved. The proposed method can be applied to build a system level power estimation environment without revealing the contents of the IP blocks inside. Thereby, it is a promising method for IP level power model construction.

• 社団法人電子情報通信学会の論文
• 2000-12-25

著者

• Shen Wen-zen

  The Department Of Electronic Engineering National Chiao-tung University

• Huang Heng-liang

  The Department Of Electronic Engineering National Chiao-tung University

• Jou Jing-yang

  The Department Of Electronic Engineering National Chiao-tung University

• Lin Jiing-yuan

  Global Unichip Corporation

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• A New Method for Constructing IP Level Power Model Based on Power Sensitivity (Special Section on VLSI Design and CAD Algorithms)
• CB-Power : A Hierarchical Power Analysis and Characterization Environment of Cell-Based CMOS Circuits (Special Section on VLSI Design and CAD Algorithms)
• Delay-Optimal Technology Mapping for Hard-Wired Non-Homogeneous FPGAs (Special Section on VLSI Design and CAD Algorithms)

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