An Efficient Approach to Build Accurate Behavioral Models of PLL Designs(<Special Section> Analog Circuit Techniques and Related Topics)
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概要
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In this paper, an efficient bottom-up extraction approach is presented to generate accurate behavioral models of PLL designs more quickly by using Verilog-AMS language. The main idea is to use a special "characterization mode" such that we can use only one input pattern to get all required circuit parameters with parasitic effects. After carefully adjustment, all parameters in our behavioral models can be measured at the outputs of the PLL system without simulating each block separately. Therefore, this approach is more suitable to accurately model protected IPs or flattened post-layout netlists. In the experimental results, we will build an accurate PLL behavioral model for demonstration and compare the results with HSPICE simulation and traditional behavioral models.
- 2006-02-01
著者
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Liu Chien-nan
The Department Of Electrical Engineering National Central University
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Liu Chien‐nan
National Central Univ. Twn
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Kuo Chin-cheng
The Department Of Electrical Engineering National Central University
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WANG Yu-Chien
the Department of Electrical Engineering, National Central University
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Wang Yu-chien
The Department Of Electrical Engineering National Central University
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