Top-Down Retargetable Framework with Token-Level Design for Accelerating Simulation Speed of Processor Architecture(Simulation Acceletor)(<Special Section>VLSI Design and CAD Algorithms)

概要

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This paper proposes a retargetable framework for rapid evaluation of processor architecture, which represents abstraction levels of architecture in a hierarchical manner. The basis for such framework is a hierarchical architecture description language, called XR^2 , which describes architecture at three abstraction levels: instruction set architecture, pipeline architecture and micro-architecture. In addition, a token-level computational model for fast pipeline simulation is proposed, which considers the minimal information required for the given performance measurement of the pipeline. Experimental result shows that token-level simulation is faster than the traditional cycle-accurate one by 50% to 80% in pipeline architecture evaluation.
一般社団法人電子情報通信学会の論文
2003-12-01