Design of High-Radix VLSI Dividers without Quotient Selection Tables(Special Section on VLSI Design and CAD Algorithms)

概要

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In this paper, we propose a unified high-radix division algorithm for high-speed signal and data processing applications, and present the design and evaluation of high-radix parallel dividers based on the proposed algorithm. By prescaling the input operands and converting some significant digits of a partial remainder into non-redundant representation, the quotient digit can be obtained directly from the partial remainder without using quotient digit selection tables. Performance evaluation shows that the proposed radix-4 and radix-8 divider architectures achieve faster computation with the same level of hardware complexity than the binary counterparts. We also show an experimental fabrication of a radix-4 divider chip in 0.35μm CMOS technology.
社団法人電子情報通信学会の論文
2001-11-01