A Reduced Bit-Width Instruction Set Architecture for FQM Execution in Hybrid Processor Architecture (FaRM-rq)

概要

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Code size is a critical concern in many applications, especially for those requiring small code size and special cores. The Queue based instruction set is a promising approach for reducing code size and system complexity. In this paper, we present an efficient narrow space instruction set architecture for a Queue mode execution (FQM) in a functional assignment register microprocessor that supports a multi instruction sets through run time functional assignment. In FQM mode, the system executes queue based instruction set (termed rwQIS) that are carefully designed with a limited opcode and access to a limited set of special registers. The rwQIS is targeted for a low system complexity and reduced Bit-Width Instructions. In addition to the instruction set architecture, we give a measure of the expressive power of FQM instruction set by the relative density and the code ratio of some benchmark programs.
一般社団法人情報処理学会の論文
2003-06-13