A Sub-Harmonic RF Transmitter Architecture with Simultaneous Power Combination and LO Leakage Cancellation
スポンサーリンク
概要
- 論文の詳細を見る
A sub-harmonic RF transmitter architecture with simultaneous power combination and carrier-leakage cancellation is proposed. It employs an 8-phase ring-type voltage controlled oscillator (VCO), sub-harmonic mixers, driver amplifiers, and a balun. A signal power is combined with its 180° phase-shifted signal through the balun. Simultaneously carrier-leakage generating in sub-harmonic mixers is canceled by its phase difference. The proposed transmitter achieved 1dBm 1-dB output compression point (P-1dB) under 1.8V supply and -40dBm carrier-leakage in 5GHz band.
- 2011-05-01
著者
-
SONG Bongsub
Dept. of ELectronic Engineering, Sogang University
-
Kim Dohyung
Mixed Signal Core Design Team Samsung Electronics
-
Song Bongsub
Dept. Of Electronic Engineering Sogang University
-
Burm Jinwook
Dept. Of Electronic Engineering Sogang University
-
Kim Kwangsoo
Sogang Institute Of Advanced Technology (siat) Sogang University
-
Kim Kwangsoo
Dept. Of Electronic Engineering Sogang University
-
KIM Dohyung
Samsung Electronics
関連論文
- A sub-harmonic RF transmitter architecture with simultaneous power combination and LO leakage cancellation (Silicon devices and materials)
- A sub-harmonic RF transmitter architecture with simultaneous power combination and LO leakage cancellation (Electron devices)
- A Sub-Harmonic RF Transmitter Architecture with Simultaneous Power Combination and LO Leakage Cancellation(Session 3B : High Speed and High Frequency Applications 1)
- A Sub-Harmonic RF Transmitter Architecture with Simultaneous Power Combination and LO Leakage Cancellation(Session 3B : High Speed and High Frequency Applications 1)
- A Phase Noise Optimized 4GHz Differential Colpitts VCO
- SiC MESFET power amplifier for 3.6GHz-3.8GHz WiMAX application(Session8B: High-Frequency, Photonic and Sensing Devices)
- SiC MESFET power amplifier for 3.6GHz-3.8GHz WiMAX application(Session8B: High-Frequency, Photonic and Sensing Devices)
- A 0.18μm CMOS over 10Gb/s 10-PAM Serial Link Receiver
- A CMOS over 12.8Gb/s 10-PAM transmitter for chip-to-chip communications
- A 0.18μm CMOS over 10Gb/s 10-PAM Serial Link Receiver
- A CMOS over 12.8Gb/s 10-PAM transmitter for chip-to-chip communications
- Chip design of a Successive Approximation A/D Converter for a Structure Monitoring System(Session8A: Si Devices III)
- Chip design of a Successive Approximation A/D Converter for a Structure Monitoring System(Session8A: Si Devices III)
- Novel 1T DRAM Cell for Low-Voltage Operation and Long Data Retention Time
- A Sub-Harmonic RF Transmitter Architecture with Simultaneous Power Combination and LO Leakage Cancellation
- A 0.18μm CMOS 12Gb/s 10-PAM Serial Link Transmitter