A Phase Noise Optimized 4GHz Differential Colpitts VCO
スポンサーリンク
概要
- 論文の詳細を見る
This letter presents the design and analysis of phase noise optimization of a 4-GHz differential Colpitts voltage-controlled-oscillator (VCO). A low phase noise is achieved by a Colpitts oscillator and a VCO bias optimization using an amplitude control method. The measured phase noise is −134.8dBc/Hz at 1.25MHz offset frequency from 4GHz operating frequency. The VCO is implemented using 0.24µm SiGe BiCMOS process with integrated copper inductors. The wide VCO frequency range covers both PCS and IMT bands and draws about 15.9mA from a 2.7V power supply.
- (社)電子情報通信学会の論文
- 2010-03-01
著者
-
AHN Hee-Tae
Dept. of Electronic Engineering, Sogang University
-
BURM Jinwook
Dept. of Electronic Engineering, Sogang University
-
Burm Jinwook
Dept. Of Electronic Engineering Sogang University
-
Ahn Hee-tae
Dept. Of Electronic Engineering Sogang University
関連論文
- A Phase Noise Optimized 4GHz Differential Colpitts VCO
- A sub-harmonic RF transmitter architecture with simultaneous power combination and LO leakage cancellation (Silicon devices and materials)
- A sub-harmonic RF transmitter architecture with simultaneous power combination and LO leakage cancellation (Electron devices)
- A Sub-Harmonic RF Transmitter Architecture with Simultaneous Power Combination and LO Leakage Cancellation(Session 3B : High Speed and High Frequency Applications 1)
- A Sub-Harmonic RF Transmitter Architecture with Simultaneous Power Combination and LO Leakage Cancellation(Session 3B : High Speed and High Frequency Applications 1)
- A Phase Noise Optimized 4GHz Differential Colpitts VCO
- SiC MESFET power amplifier for 3.6GHz-3.8GHz WiMAX application(Session8B: High-Frequency, Photonic and Sensing Devices)
- SiC MESFET power amplifier for 3.6GHz-3.8GHz WiMAX application(Session8B: High-Frequency, Photonic and Sensing Devices)
- A 0.18μm CMOS over 10Gb/s 10-PAM Serial Link Receiver
- A CMOS over 12.8Gb/s 10-PAM transmitter for chip-to-chip communications
- A 0.18μm CMOS over 10Gb/s 10-PAM Serial Link Receiver
- A CMOS over 12.8Gb/s 10-PAM transmitter for chip-to-chip communications
- Chip design of a Successive Approximation A/D Converter for a Structure Monitoring System(Session8A: Si Devices III)
- Chip design of a Successive Approximation A/D Converter for a Structure Monitoring System(Session8A: Si Devices III)
- A Sub-Harmonic RF Transmitter Architecture with Simultaneous Power Combination and LO Leakage Cancellation