A 0.18μm CMOS over 10Gb/s 10-PAM Serial Link Receiver
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概要
- 論文の詳細を見る
A multi Gb/s multi-level pulse amplitude modulation (PAM) receiver for chip to chip communication is proposed. Increasing data bit rate is achieved with 10-PAM. To increase data bit-rate and reduce BER, We designed this circuit by using a current mode amplifier, CML circuit. The 10-PAM receiver is designed in 0.18μm CMOS technology and achieves Gb/s of data bit rates. The simulated BER is less than 1.0×10^<-12>. The simulation results showed that the 0.5×0.6mm^2 chip consumes 57mA at 12.8Gb/s from a 1.8-V supply.
- 社団法人電子情報通信学会の論文
- 2009-06-17
著者
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BURM Jinwook
Dept. of Electronic Engineering, Sogang University
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Burm Jinwook
Sogang Univ. Seoul Kor
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Burm Jinwook
Dept. Of Electronic Engineering Sogang University
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Lee Jeongjun
Dept. of Electronic Engineering, Sogang University
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Jeong Jikyung
Dept. of Electronic Engineering, Sogang University
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Lee Jeongjun
Dept. Of Electronic Engineering Sogang University
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Jeong Jikyung
Dept. Of Electronic Engineering Sogang University
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