Novel 1T DRAM Cell for Low-Voltage Operation and Long Data Retention Time

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概要

• 論文の詳細を見る

• A novel one-transistor dynamic random access memory (1T DRAM) cell has been proposed for a low-voltage operation and longer data retention time. The proposed 1T DRAM cell has three features compared with a conventional 1T DRAM cell: low body doping concentration, a recessed gate structure, and a P+ poly-Si gate. Simulation results show that the proposed 1T DRAM cell has < 1-ns program time and > 100-ms data retention time under the condition of sub-1-V operating voltage.

• （社）電子情報通信学会の論文
• 2011-01-01

著者

• KIM Kwangsoo

  Sogang Institute of Advanced Technology (SIAT), Sogang University

• Lee Woojun

  The Department Of Electronic Engineering Sogang University

• Choi Woo

  The Department Of Electronic Engineering Sogang University

• Kim Kwangsoo

  Sogang Institute Of Advanced Technology (siat) Sogang University

• Kim Kwangsoo

  Dept. Of Electronic Engineering Sogang University

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