Code Compression with Split Echo Instructions

スポンサーリンク

概要

• 論文の詳細を見る

• Code density is often a critical issue in embedded computers, since the memory size of embedded systems is strictly limited. Echo instructions have been proposed as a method for reducing code size. This paper presents a new type of echo instruction, split echo, and evaluates an implementation of both split echo and traditional echo instructions on a MIPS R3000 based processor. Evaluation results show that memory requirement is reduced by 12% on average with small additional hardware cost.

• （社）電子情報通信学会の論文
• 2009-09-01

著者

• STUBDAL Iver

  Keio University

• KARADUMAN Arda

  Keio University

• AMANO Hideharu

  Keio University

• Amano Hideharu

  Keio Univ.

関連論文

• Code Compression with Split Echo Instructions
• Code Compression with Split Echo Instructions
• Performance Evaluation of Hardware Multi-process Execution on the Dynamically Reconfigurable Processor
• Automatic Pipeline Construction Focused on Similarity of Rate Law Functions for an FPGA-based Biochemical Simulator
• Architecture and Evaluation of a Third-Generation RHiNET Switch for High-Performance Parallel Computing( Development of Advanced Computer Systems)
• An FPGA-Based Acceleration Method for Metabolic Simulation(Recornfigurable Systems)(Reconfigurable Systems)
• A Retargetable Compiler Based on Graph Representation for Dynamically Reconfigurable Processor Arrays
• Performance Evaluation of 3-Dimensional MIN with Cache Consistency Maintenance Mechanism
• Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units
• Design and Implementation of Echo Instructions for an Embedded Processor

スポンサーリンク