Low Threshold Voltage Gate-First pMISFETs with Poly-Si/TiN/HfSiON Stacks Fabricated with PVD-based In-situ Solid Phase Interface Reaction (SPIR) Method

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2007-09-19

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Systematic studies on Fermi level pining of Hf-based high-k gate stacks
Low Threshold Voltage Gate-First pMISFETs with Poly-Si/TiN/HfSiON Stacks Fabricated with PVD-based In-situ Solid Phase Interface Reaction (SPIR) Method
Phase and Composition Control of Ni-FUSI gates by N_2 I/I with Double Ni-silicidation
Diffusion control technique in TiN stacked metal gate electrodes for p-MISFETs
The Impact of Thickness Control in HfSiON Gate Dielectric on Electron Mobility with sub-nm EOT

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