NBTI Improvement under Highly Compressive Contact Etching Stop Layer (CESL) for 45nm Node CMOS and Beyond

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2006-09-13

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NBTI Improvement under Highly Compressive Contact Etching Stop Layer (CESL) for 45nm Node CMOS and Beyond
56% pMOSFETs Drive Current Enhancement from Optimized Compressive Contact Etching Stop Layer (CESL) for 45nm Node CMOS
Impact of Reducing Shallow Trench Isolation Mechanical Stress on Active Length for 40 nm n-Type Metal--Oxide--Semiconductor Field-Effect Transistors
Investigation of Stress Memorization Process on Low-Frequency Noise Performance for Strained Si n-Type Metal--Oxide--Semiconductor Field-Effect Transistors
Effect of STI Stress Enhanced Boron Diffusion on Leakage and Vcc min of Sub-65nm node Low-Power SRAM
A High Gain (25%) Strained Silicon Scheme for 65nm High Performance nMOSFETs
New Negative-Bias-Temperature-Instability Improvement Using Buffer Layer under Highly Compressive Contact Etch Stop Layer for 45-nm-Node Complementary Metal–Oxide–Semiconductor and Beyond

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