A High Gain (25%) Strained Silicon Scheme for 65nm High Performance nMOSFETs
スポンサーリンク
概要
- 論文の詳細を見る
- 2005-09-13
著者
-
HUANG C
United Microelectronics Corp. (UMC), CRD Logic Division
-
Tsai C
United Microelectronics Corporation (umc) Central R&d Division
-
Pan J
United Microelectronics Corporation (umc) Central R&d Division
-
CHANG T
United Microelectronics Corporation (UMC), Central R&D Division
-
LIU Y
United Microelectronics Corporation (UMC), Central R&D Division
-
LIU P
United Microelectronics Corporation (UMC), Central R&D Division
-
LAN B
United Microelectronics Corporation (UMC), Central R&D Division
-
CHEN T
United Microelectronics Corporation (UMC), Central R&D Division
-
TUNG C
United Microelectronics Corporation (UMC), Central R&D Division
-
SHIAU W
United Microelectronics Corporation (UMC), Central R&D Division
-
Shiau W
United Microelectronics Corporation (umc) Central R&d Division
-
Tung C
United Microelectronics Corporation (umc) Central R&d Division
-
LIU Y
United Microelectronics Corporation (UMC), Central R&D Division
-
CHEN T
United Microelectronics Corporation (UMC), Central R&D Division
関連論文
- NBTI Improvement under Highly Compressive Contact Etching Stop Layer (CESL) for 45nm Node CMOS and Beyond
- A High Gain (25%) Strained Silicon Scheme for 65nm High Performance nMOSFETs