SET/CMOS Hybrid Integration Process for Multiple-Valued Logics
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概要
- 論文の詳細を見る
- 2004-09-15
著者
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LEE J.
School of Elec. Eng. and Computer Science, Kyungpook National Univ.
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Park B.-g.
School Of Electrical Eng. Seoul National Univ.
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Park B.-g.
School Of Electrical Engineering Eng420-016 Seoul National University
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Kim K.
School Of Mechanical Engineering Pusan National University
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Lee J.
School Of Advanced Materials Science And Engineering And Skku Advanced Institute Of Nanotechnology S
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LEE Y.
School of Mechanical Engineering, Pukyong National University
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Kim Y.-w.
R&d Center Samsung Electronics Co.
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SONG K.-W.
School of Electrical Engineering ENG420-016, Seoul National University
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HUH J.
School of Electrical Engineering ENG420-016, Seoul National University
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HAN J.
R&D Center, Samsung Electronics Co.
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KIM Y.-W.
R&D Center, Samsung Electronics Co.
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Lee Y.
School Of Earth And Environmental Sciences Seoul National University
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Kim K.
School Of Electrical Engineering And Computer Science Kyungpook National University
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Song K.-w.
School Of Electrical Engineering Eng420-016 Seoul National University
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Kim K.
School Of Electrical Engineering Eng420-016 Seoul National University
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Lee Y.
School Of Electrical Engineering Eng420-016 Seoul National University
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Huh J.
School Of Electrical Engineering Eng420-016 Seoul National University
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