A 1-Dimensional Chaotic IC Designed by SI Techniques
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概要
- 論文の詳細を見る
In this paper, a VLSI chip of a discrete-time chaos circuit realizing a tent map is reported. The VLSI chip is fabricated in the chip fabrication program of VLSI Design and Education Center (VDEC). A simple structure enables us to realize the circuit with 10 MOSFET’s and 2 capacitors. Furthermore, the circuit which is designed by switched-current (SI) techniques can operate at 3V power supply. The experiment concerning the VLSI chip shows that the proposed circuit is integrable by a standard 1.2 μm CMOS technology.
- 社団法人 電気学会の論文
- 2003-09-01
著者
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Eguchi Kei
Department of Technology Education, Shizuoka University
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Inoue T
Kumamoto University
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Inoue Takahiro
Kumamoto University
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Inoue T
Faculty Of Engineering Kumamoto University
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Inoue Takahiro
Dep. Of Computer Sci. And Electrical Engineering Graduate School Of Sci. And Technol. Kumamoto Univ.
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Zhu Hongbing
Department Of Computer Science Faculty Of Engineering Hiroshima Kokusai Gakuin University
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EGUCHI Kei
Kumamoto National College of Technology
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TABATA Toru
Kumamoto National College of Technology
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UENO Fumio
Sojo University
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ZHU Hongbing
Hiroshima Kokusai Gakuin University
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Eguchi Kei
Department Of Information And Computer Sciences Kumamoto National College Of Technology
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Eguchi Kei
Department Of Technology Education Shizuoka University
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Eguchi Kei
The Department Of Electrical Engineering And Computer Science Kumamoto University
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Inoue T
Graduate School Of Science And Technology Kumamoto University
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Ueno F
National Coll. Technol. Kumamoto‐ken Jpn
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