Boltzmann Machine Processor Using Single-Bit Operation (Special Section on JTC-CSCC '92)
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概要
- 論文の詳細を見る
This paper describes a single-bit parallel processor specified to Boltzmann Machine. The processor has SIMD (Single Instruction Multiple Data stream) type parallel architecture and every processing element (PE) has a single-bit ALU and a local memory storing connected weights between neurons. Features of the processor are large scale parallel processing using a number of the simple single-bit PEs and effective expansion realized by multiple chips connected simple bus lines. Moreover, it is enhanced that the processing speed can be independent of the number of the neurons. We designed the PE using 1.2 μm CMOS process standard cells and confirmed the high performance using CAD simulations.
- 社団法人電子情報通信学会の論文
- 1993-06-25
著者
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Sasaki Mamoru
The Faculty Of Engineering Kumamoto University
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Sasaki M
Faculty Of Engineering Kumamoto University
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Ueno Fumio
the Faculty of Engineering, Kumamoto University
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Inoue Takahiro
the Faculty of Engineering, Kumamoto University
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Sasaki Masafumi
Department Of Electrical Engineering The National Defense Academy
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UENO Fumio
Sojo University
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Ueno Fumio
The Faculty Of Engineering Kumamoto University
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Sasaki Mamoru
Dept. Of Electrical And Computer Engineering Faculty Of Engineering Kumamoto University
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Kaneda Shuichi
the Faculty of Engineering, Kumamoto University
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Kitamura Yoshiki
the Faculty of Engineering, Nippon Bunri University
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Ueno F
National Coll. Technol. Kumamoto‐ken Jpn
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Kaneda Shuichi
The Faculty Of Engineering Kumamoto University
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Kitamura Yoshiki
The Faculty Of Engineering Nippon Bunri University
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Inoue Takahiro
The Faculty Of Engineering Kumamoto University
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