An FPGA-implementable chaos circuit with array structure
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概要
- 論文の詳細を見る
- 2002-03-01
著者
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Eguchi Kei
Department of Technology Education, Shizuoka University
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Inoue T
Kumamoto University
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Inoue Takahiro
Kumamoto University
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Inoue T
Faculty Of Engineering Kumamoto University
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Inoue Takahiro
Dep. Of Computer Sci. And Electrical Engineering Graduate School Of Sci. And Technol. Kumamoto Univ.
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Zhu Hongbing
Department Of Computer Science Faculty Of Engineering Hiroshima Kokusai Gakuin University
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EGUCHI Kei
Kumamoto National College of Technology
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TABATA Toru
Kumamoto National College of Technology
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UENO Fumio
Sojo University
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ZHU Hongbing
Hiroshima Kokusai Gakuin University
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Eguchi Kei
Department Of Information And Computer Sciences Kumamoto National College Of Technology
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Eguchi Kei
Department Of Technology Education Shizuoka University
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Eguchi Kei
The Department Of Electrical Engineering And Computer Science Kumamoto University
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Inoue T
Graduate School Of Science And Technology Kumamoto University
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Ueno F
National Coll. Technol. Kumamoto‐ken Jpn
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