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School Of Electrical Engineering Seoul National University | 論文
- Simulation of High Energy E-beam Lithography for Nano-Patterning : A Development of E-beam Lithography Simulator(Session A8 Nano-Lithography)(2004 Asia-Pasific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
- Simulation of High Energy E-beam Lithography for Nano-Patterning : A Development of E-beam Lithography Simulator(Session A8 Nano-Lithography)(2004 Asia-Pasific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
- Simulation of High Energy E-beam Lithography for Nano-Patterning : A Development of E-beam Lithography Simulator
- Simulation of High Energy E-beam Lithography for Nano-Patterning : A Development of E-beam Lithography Simulator
- A New Micromachining Technique with (111) Silicon
- Electric Field Optimization in 170kV Gas-Insulated Switchgear Spacer based on Non-Uniform Rational B-spline Curve
- Packet Error Rate Analysis of IEEE802.15.4 under Saturated IEEE802.11b Network Interference(Network)
- Anisotropic Bulk Etching of (110) Silicon with High Aspect Ratio
- A Insitu Vacuum Encapsulated Novel Lateral Field Emitter Triode with Titanium Cathode
- Simulation Study on Dependence of Channel Potential Self-Boosting on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
- Simulation of Gate-All-Around Tunnel Field-Effect Transistor with an n-Doped Layer
- Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory
- 3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array
- Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation
- Application of the Compact Channel Thermal Noise Model of Short Channel MOSFETs to CMOS RFIC Design
- Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme
- Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)
- Electrical Breakdown Voltage In a Mixed Gas : Nuclear Science, Plasmas, and Electric Discharges
- Complementary Self-Biased Logics Based on Single-Electron Transistor (SET)/CMOS Hybrid Process
- Channel Doping Engineering with Indium as an Alternative p-Type Dopant