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Ntt Basic Research Laboratories Ntt Cornoration | 論文
- Single-electron transfer in phosphorous-doped Si nanowire FETs
- Time-controlled single-electron transfer in single-gated asymmetric multiple tunnel junction arrays
- Formation of Nanometer-Scale Dislocation Network Sandwiched by Silicon-on-Insulator Layers
- A Single-Electron-Transistor Logic Gate Family for Binary, Multiple-Valued and Mixed-Mode Logic(New System Paradigms for Integrated Electronics)
- A Simulation Methodology for Single-Electron Multiple-Valued Logics and Its Application to a Latched Parallel Counter
- Novel-Functional Single-Electron Devices Using Silicon Nanodot Array
- Fabrication of double-dot single-electron transistor in silicon nanowire
- Novel-Functional Single-Electron Devices Using Silicon Nanodot Array
- Fabrication of double-dot single-electron transistor in silicon nanowire
- Single-Electron-Resolution Electrometer Based on Field-Effect Transistor(Session4B: Emerging Devices II)
- Single-Electron-Resolution Electrometer Based on Field-Effect Transistor(Session4B: Emerging Devices II)
- Capacitive Parameter Extraction for Nanometer-Size Field-Effect Transistors
- Transfer and Detection of Single Electrons Using Metal-Oxide-Semiconductor Field-Effect Transistors(Emerging Devices,Fundamentals and Applications of Advanced Semiconductor Devices)
- Charge-State Control of Phosphorus Donors in Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect Transistor
- Multifunctional Boolean Logic Using Single-Electron Transistors(New System Paradigms for Integrated Electronics)
- A Multiple-Valued Logic and Memory With Combined Single-Electron and Metal-Oxide-Semiconductor Transistors
- A Merged Single-Electron Transistor and Metal-Oxide-Semiconductor Transistor Logic for Interface and Multiple-Valued Functions
- Multipeak negative-differential-resistance device by combining single-electron and metal-oxide-semiconductor transistors
- A Merged SET-MOSFET Logic for Interface and Multiple-Valued Functions
- Time-controlled single-electron transfer in single-gated asymmetric multiple tunnel junction arrays