スポンサーリンク
Inter-university Semiconductor Research Center (ISRC) and School of Electrical Engineering, Seoul National University, San 56-1, Sillim-dong, Gwanak-gu, Seoul 151-742, Republic of Korea | 論文
- A New Cone-Type 1T DRAM Cell(Session 2A : Memory 1)
- A New Cone-Type 1T DRAM Cell(Session 2A : Memory 1)
- Charge Injection Path of Bottom-Contact Organic Thin-Film Transistors(Session4B: Emerging Devices II)
- Charge Injection Path of Bottom-Contact Organic Thin-Film Transistors(Session4B: Emerging Devices II)
- An Analytic Current-Voltage Equation for Top-contact OTFTs Including the Effects of Variable Series Resistance
- Threshold Voltage Roll-off Mechanisms in SONOS Flash Memory in Retention Mode Including Trapped Charge Redistribution Effect(Session 2A : Memory 1)
- Threshold Voltage Roll-off Mechanisms in SONOS Flash Memory in Retention Mode Including Trapped Charge Redistribution Effect(Session 2A : Memory 1)
- Multi-level reading method by using PCI (Paired Cell Interference) in vertical NAND flash memory
- Multi-level reading method by using PCI (Paired Cell Interference) in vertical NAND flash memory
- Simulation of Retention Characteristics in Double-Gate Structure Multi-bit SONOS Flash Memory(Session4A: Nonvolatile Memory)
- Simulation of Retention Characteristics in Double-Gate Structure Multi-bit SONOS Flash Memory(Session4A: Nonvolatile Memory)
- Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory
- Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme
- Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)
- Program/Erase Model of Nitride-Based NAND-Type Charge Trap Flash Memories
- Room-Temperature Operation of a Single-Electron Transistor Made by Oxidation Process Using the Recessed Channel Structure
- An Analytic Current–Voltage Equation for Top-Contact Organic Thin Film Transistors Including the Effects of Variable Series Resistance