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Inter-University Semiconductor Research Center, Seoul National University | 論文
- Nanoscale Poly-Si Line Formation and Its Uniformity
- Nanoscale Poly-Si Line Formation and Its Uniformity
- Design and Simulation of Asymmetric MOSFETs(Junction Formation and TFT Reliability,Fundamentals and Applications of Advanced Semiconductor Devices)
- Novel Gate-All-Around MOSFETs with Self-Aligned Structure
- Multi-Functionality of Novel Structured Tunneling Devices
- Junction Leakage Characteristics of Shallow Trench Isolation (STI) with Nitrogen Pile-Up Sidewall Oxide(AWAD2003 : Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices)
- Junction Leakage Characteristics of Shallow Trench Isolation (STI) with Nitrogen Pile-Up Sidewall Oxide(AWAD2003 (Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices))
- Design and Simulation of Asymmetric MOSFETs(Session 7A Silicon Devices IV,AWAD2006)
- Design and Simulation of Asymmetric MOSFETs(Session 7A Silicon Devices IV,AWAD2006)
- Design and Simulation of Asymmetric MOSFETs
- Integration Process of Impact-Ionization Metal-Oxide-Semiconductor Devices with Tunneling Field-Effect-Transistors and Metal-Oxide-Semiconductor Field-Effect Transistors
- Stable Extraction of Threshold Voltage Using Transconductance Change Method for CMOS Modeling, Simulation and Characterization
- Reverse-Order Source/Drain with Double Offset Spacer (RODOS) for Sub-5Onm Low-Power and High-Speed MOSFET Design(AWAD2003 : Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices)
- Reverse-Order Source/Drain with Double Offset Spacer (RODOS) for Sub-50nm Low-Power and High-Speed MOSFET Design (AWAD2003 (Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices))
- Side-Gate Design for 50nm Electrically Induced Source/Drain MOSFETs
- Side-gate Length Optimization for 50nm Induced Source/Drain MOSFETs
- 70nm NMOSFET Fabrication with 12nm n^+-p Junctions Using As^+_2 Low Energy Implantations
- 70nm NMOSFET Fabrication with 12nm n^+-p Junctions Using As_2^+ Å Low Energy Ion Implantations
- Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL)
- Properties of the p^+ poly-Si Gate Fabricated Using the As Preamorphization Method