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Division Of Electrical Electronics And Information Engineering Graduate School Of Engineering Osaka | 論文
- CMOS Front-End Circuits of Dual-Band GPS Receiver(RF, Analog Circuit and Device Technologies)
- Ultralow-Power Current Reference Circuit with Low Temperature Dependence(Building Block, Analog Circuit and Device Technologies)
- A CMOS IF Variable Gain Amplifier with Exponential Gain Control(Analog Circuit Techniques and Related Topics)
- High Speed and Noise Tolerant Parallel Bus Interface for VLSI Systems Using Multi Bit Code Division Multiple Access(New System Paradigms for Integrated Electronics)
- Watch-Dog Circuit for Quality Guarantee with Subthreshold MOSFET Current(New System Paradigms for Integrated Electronics)
- CMOS Demodulator for Short-Range Wireless Interconnection Using ASK/CDMA Technique(Wide Band Systems)
- Watchdog Circuit for Product Degradation Monitor using Subthreshold MOS Current
- A New Analog Correlator Circuit for DS-CDMA Wireless Applications
- Dynamically Programmable Paralell Processor (DPPP) : A Novel Reconfigurable Architecture with Simple Program Interface(Special Issue on Function Integrated Information Systems)
- Error Analysis on Simultaneous Data Transfers in CDMA Wired Interface
- C-12-26 An Auto-sensitivity Control Circuit for DS-CDMA Receiver Circuit
- A Novel Dynamically Programmable Arithmetic Array(DPAA)Processor for Digital Signal Processing(Special Section of Selected Papers from the 13th Workshop on Circuits and Systems in Karuizawa)
- Poly-Si TFTにおけるゲート酸化膜へのホットホール注入と捕獲/放出特性の評価(シリコン関連材料の作製と評価)
- A 10-bit 800-Column Low-Power RAM Bank Including Energy-Efficient D-Flip-Flops for a Column-Parallel ADC(Analog Circuit Techniques and Related Topics)
- Design of a 0.5V Op-Amp Based on CMOS Inverter Using Floating Voltage Sources
- Low-Voltage Wireless Analog CMOS Circuits toward 0.5V Operation
- Application of Noise-Enhanced Detection of Subthreshold Signals for Communication Systems
- A New Inductance Extraction Technique of On-Wafer Spiral Inductor Based on Analytical Interconnect Formula(Microelectronic Test Structures)
- A Low-Voltage SOI-CMOS LC-Tank VCO with Double-Tuning Technique Using Lateral P-N Junction Variable Capacitance(Special lssue on Silicon RF Device & Integrated Circuit Technologies)
- A-3-1 A 5Msample/s 0.965-mW Switched-Capacitor Filter in 0.6-μm CMOS Technology