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Dept. Of Computer Science And Technology Tsinghua National Laboratory For Information Science And Te | 論文
- Low Power Gated Clock Tree Driven Placement
- Efficient Power Network Analysis with Modeling of Inductive Effects
- Efficient Partial Reluctance Extraction for Large-Scale Regular Power Grid Structures
- Logic and Layout Aware Level Converter Optimization for Multiple Supply Voltage
- Stochastic Interconnect Tree Construction Algorithm with Accurate Delay and Power Consideration(VLSI Design Technology and CAD)
- Voltage Island Generation in Cell Based Dual-Vdd Design(VLSI Design Technology and CAD)
- Navigating Register Placement for Low Power Clock Network Design(Floorplan and Placement, VLSI Design and CAD Algorithms)
- A Fast Delay Computation for the Hybrid Structured Clock Network(VLSI Design Technology and CAD)
- Crosstalk and Congestion Driven Layer Assignment Algorithm(Circuit Theory)
- Accurate Eye Diagram Prediction Based on Step Response and Its Application to Low-Power Equalizer Design