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Department Of Electronics Engineering National Chiao Tung University | 論文
- Dimensional Effects on the Drain Current of N-and P-Channel Polycrystalline Silicon Thin Film Transistors
- Excellent Au/Ge/Pd Ohmic Contacts to n-type GaAs Using Mo/Ti as the Diffusion Barrier
- High-Performance Au/Ti/Ge/Pd Ohmic Contacts on n-Type In_Ga_P
- New Polysilicon-Oxide-Nitride-Oxide-Silicon Electrically Erasable Programmable Read-only Memory Device Approach for Eliminating Off-Cell Leakage Current
- Growth of ZnSe Epilayer on Si Using Ge/Ge_xSi_ Buffer Structure
- Generalized Interconnect Delay Time and Crosstalk Models: II. Crosstalk-Induced Delay Time Deterioration and Worst Crosstalk Models : Semiconductors
- Generalized Interconnect Delay Time and Crosstalk Models: I. Applications of Interconnect Optimization Design : Semiconductors
- Sequence polymorphism in the mtDNA HV1 region in Japanese and Chinese
- Optimization of Short Channel Effect With Arsenic Halo Implant through Polysilicon Gate : Semiconductors
- Shallow-Trench Isolation With Raised-Field-Oxide Structure
- Joint Low-Complexity Blind Equalization, Carrier Recovery, and Timing Recovery with Application to Cable Modem Transmission
- Multi-Gigabit Pre-Emphasis Design and Analysis for Serial Link(Electronic Circuits)
- Performance of AlGaN/GaN Heterostrucrure FETs Over Temperatures
- Temperature-Dependent Electron Transport Properties of AlGaN/GaN Heterostructures
- Pharmacokinetic study of three cardiovascular drugs by high-performance liquid chromatography using pre-column derivatization with 9,10-anthraquinone-2-sulfonyl chloride
- Development and evaluation of an efficient HPLC/MS/MS method for the simultaneous determination of pseudoephedrine and cetirizine in human plasma : Application to Phase-I pharmacokinetic study
- The Elimination of Inversion Domains in MBE-GaN Grown Using Low Temperature Nitridation
- Measurement of Thin Oxide Films on Implanted Si-Substrate by Ellipsometry
- A Study on Bilateral Latch-Up Self-Triggering in Complementary Metal-Oxide-Semiconductor Protection Circuits
- The Behavior of Bilateral Latch-Up Triggering in VLSI Electro Static Discharge Damage Protection Circuits