Hirabayashi Atsuo | Advanced Device Technology Laboratory Fuji Electric Corporate R Amp Ltd.

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著作論文

Measurements of the Breakdown Voltage of the Lateral Insulated Gate Bipolar Transistor on the Silicon-on-Insulator Film with Varying Implantation Doses for the N-Buffer Layer
SOI LIGBT Structure with the Collector-Short Region for Improved Latch-Up Performance
Investigation of Transient Substrate Currents in Lateral Power Devices on Silicon-on-Insulator
Noise Current Induced by Switching of a Dielectric Isolated Lateral Insulated Gate Bipolar Transistor on Silicon-on-Insulator
A Lateral Insulated Gate Bipolar Transistor Structure with the Collector-Short Region for Improved Latch-Up Performance
Long-Term Reliability of the Blocking Capability and Failure Voltage of Electrostatic Discharge of the SOI High-Voltage Device and IC
Long-Term Reliability of the Blocking Capability and Failure Voltage of Electrostatic Discharge(ESD) of SOI High-Voltage Device and IC
Measurement of the Breakdown Voltage of Lateral Power Metal-Oxide-Semiconductor Field-Effect-Transistors on a Silicon-on-Insulator Film with Varying the Surface Design around the Gate Region
Lateral IGBT Structure on the SOI Film with the Collector-Short Region for Improved Blocking Capability

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