Patterning of Two-Dimensional Graphene Oxide on Silicon Substrates
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概要
- 論文の詳細を見る
Chemically synthesized graphene is promising for device applications because the chemical approach enables ease of mass production and chemical modification of its properties. However, a major drawback of graphene based devices is that it is difficult to integrate the small flakes of graphene into device architectures. In order to overcome this limitation, we describe a simple procedure for patterning graphene oxide (GO) flakes onto predefined locations of silicon substrates. We exploited the negatively charged surface of GO flakes, and successfully patterned GO flakes onto photolithographically defined positively charged regions on silicon substrates. We demonstrate the simultaneous fabrication of multiple GO flakes device structures by controlling the surface chemistry of substrates. Our procedure for the precise positioning of GO flakes will be an important step in the fabrication of graphene devices.
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2010-06-25
著者
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Morimoto Yoshitaka
Department Of Applied Chemistry Faculty Of Engineering Osaka Institute Of Technology
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Adarsh Sandhu
Department of Electrical and Electronic Engineering, Tokyo Institute of Technology, 2-12-1 O-okayama, Meguro, Tokyo 152-8552, Japan
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Adarsh Sandhu
Department of Electrical and Electric Engineering, Tokyo Institute of Technology, 2-12-1 O-okayama, Meguro, Tokyo 152-8552, Japan
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Masashi Bando
Department of Electrical and Electronic Engineering, Tokyo Institute of Technology, 2-12-1 O-okayama, Meguro, Tokyo 152-8552, Japan
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Bando Masashi
Department of Electrical and Electronic Engineering, Tokyo Institute of Technology, Meguro, Tokyo 152-8552, Japan
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Ishikawa Ryousuke
Department of Electrical and Electronic Engineering, Tokyo Institute of Technology, Meguro, Tokyo 152-8552, Japan
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Sang Yoon
G-COE Program on Evolving Education and Research Center for Spatio-Temporal Biological Network, Tokyo Institute of Technology, 2-12-1 O-okayama, Meguro, Tokyo 152-8552, Japan
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Ryousuke Ishikawa
Department of Electrical and Electronic Engineering, Tokyo Institute of Technology, 2-12-1 O-okayama, Meguro, Tokyo 152-8552, Japan
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Yoshitaka Morimoto
Department of Electrical and Electronic Engineering, Tokyo Institute of Technology, 2-12-1 O-okayama, Meguro, Tokyo 152-8552, Japan
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