Comparison of Lifetime Improvements in Electromigration between Ti Barrier Metal and Chemical Vapor Deposition Co Capping
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概要
- 論文の詳細を見る
As promising technologies for fabrication of highly reliable Cu interconnects, using Ti barrier metal (Cu/Ti) and chemical vapor deposition (CVD) Co capping (Co/Cu/Ta/TaN) were compared. Both Cu interconnects similarly showed longer electromigration (EM) lifetime and larger activation energy of lifetime than conventional Cu interconnects fabricated using Ta/TaN barrier metal without capping metal (Cu/Ta/TaN). The residual resistance of Cu lines was measured cryogenically. Cu/Ti showed a higher residual resistance than Co/Cu/Ta/TaN and Cu/Ta/TaN, which indicates the presence of more impurities and a higher density of grain boundaries in Cu/Ti. Energy dispersive X-ray spectroscopy (EDX) analysis showed that a large amount of Ti doped into the Cu line segregated mostly at the grain boundaries on the Cu surface. It is suggested that Ti doped into a Cu line suppresses Cu diffusion through only the grain boundaries on the Cu surface. On the other hand, Co capping suppresses Cu diffusion through the entire Cu surface. As Cu/Ti improved EM lifetime significantly, the grain boundaries on the Cu surface are proposed to be a predominant diffusion path in EM. Since the density of grain boundaries probably increases on the Cu surface as interconnects shrink, suppressing the grain boundary diffusion on the Cu surface is highly effective to strengthen EM reliability.
- 2010-04-25
著者
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Kakuhara Yumi
Advanced Device Development Division, NEC Electronics Corporation, 1120 Shimokuzawa, Sagamihara, Kanagawa 229-1198, Japan
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Yumi Kakuhara
Advanced Device Development Division, NEC Electronics Corporation, 1120 Shimokuzawa, Sagamihara, Kanagawa 229-1198, Japan
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Yokogawa Shinji
Advanced Device Development Division, NEC Electronics Corporation, 1120 Shimokuzawa, Sagamihara, Kanagawa 229-1198, Japan
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Ueno Kazuyoshi
Department of Electronic Engineering, Shibaura Institute of Technology, Koto, Tokyo 135-8548, Japan
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Kazuyoshi Ueno
Department of Electronic Engineering, Shibaura Institute of Technology, Koto, Tokyo 135-8548, Japan
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