Deposition-Temperature Effect on Nitride Trapping Layer of Silicon–Oxide–Nitride–Oxide–Silicon Memory

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概要

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• A silicon nitride film is one of the most important factors for determining the trapping efficiency of nonvolatile silicon–oxide–nitride–oxide–silicon (SONOS) memory devices. In this work, we focus on the nitride-layer deposition at different temperatures by low-pressure chemical vapor deposition (LPCVD) and examine the trap levels through photoluminescence (PL) measurement. Moreover, using DC current–voltage ($I$–$V$) and capacitance–voltage ($C$–$V$) measurements, we investigate the electrical characteristics, breakdown characteristics, and the relationship between performance and trap-level depth. Our results show that the silicon nitride deposited by LPCVD at 830 °C has better performance and reliability. However, the charge-to-breakdown ($Q_{\text{BD}}$) quality of the nitride film deposited at 600 °C is better due to the suppression of the influence of the transition layer near the interface at the lower deposition temperature. In summary, this study can help researchers to understand the temperature effect on nitride-film deposition and the analysis of its electrical characteristics.

• Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
• 2007-05-15

著者

• Kao Chin-hsing

  Department Of Applied Physics Chung-cheng Institute Of Technology National Defense University

• Wu Cheng-Yen

  Semiconductor Laboratory, Chung-Cheng Institute of Technology, National Defense University, Tahsi, Taoyuan 335, Taiwan, R.O.C.

• Wu Jia-Lin

  School of Defense Science, Chung-Cheng Institute of Technology, National Defense University, Tahsi, Taoyuan 335, Taiwan, R.O.C.

• Chien Hua-Ching

  Semiconductor Laboratory, Chung-Cheng Institute of Technology, National Defense University, Tahsi, Taoyuan 335, Taiwan, R.O.C.

• Wang Je-Chuang

  Department of Applied Physics, Chung-Cheng Institute of Technology, National Defense University, Tahsi, Taoyuan 335, Taiwan, R.O.C.

• Kao Chin-Hsing

  Department of Applied Physics, Chung-Cheng Institute of Technology, National Defense University, Tahsi, Taoyuan 335, Taiwan, R.O.C.

関連論文

• Deposition-Temperature Effect on Nitride Trapping Layer of Silicon–Oxide–Nitride–Oxide–Silicon Memory
• High-$Q$ Spiral Inductor Design on Silicon Substrate
• Endurance and Data Retention Improvement of Silicon–Oxide–Nitride–Oxide–Silicon Nonvolatile Semiconductor Memory Devices with Partially Bottom-Silicon-Rich Nitride Structure
• Retention Reliability Improvement of Silicon–Oxide–Nitride–Oxide–Silicon Nonvolatile Memory with N2O Oxidation Tunnel Oxide

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