Chien Hua-Ching | Semiconductor Laboratory, Chung-Cheng Institute of Technology, National Defense University, Tahsi, Taoyuan 335, Taiwan, R.O.C.
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概要
- Chien Hua-Chingの詳細を見る
- 同名の論文著者
- Semiconductor Laboratory, Chung-Cheng Institute of Technology, National Defense University, Tahsi, Taoyuan 335, Taiwan, R.O.C.の論文著者
関連著者
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Wu Jia-Lin
School of Defense Science, Chung-Cheng Institute of Technology, National Defense University, Tahsi, Taoyuan 335, Taiwan, R.O.C.
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Chien Hua-Ching
Semiconductor Laboratory, Chung-Cheng Institute of Technology, National Defense University, Tahsi, Taoyuan 335, Taiwan, R.O.C.
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Kao Chin-hsing
Department Of Applied Physics Chung-cheng Institute Of Technology National Defense University
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Wu Cheng-Yen
Semiconductor Laboratory, Chung-Cheng Institute of Technology, National Defense University, Tahsi, Taoyuan 335, Taiwan, R.O.C.
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Wang Je-Chuang
Department of Applied Physics, Chung-Cheng Institute of Technology, National Defense University, Tahsi, Taoyuan 335, Taiwan, R.O.C.
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Kao Chin-Hsing
School of Defense Science, Chung-Cheng Institute of Technology, National Defense University, Tahsi, Taoyuan 335, Taiwan, R.O.C.
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Tsai Tzung-Kuen
Semiconductor Laboratory, Chung-Cheng Institute of Technology, National Defense University, Tahsi, Taoyuan 335, Taiwan, R.O.C.
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Liao Chien-Wei
Semiconductor Laboratory, Chung-Cheng Institute of Technology, National Defense University, Tahsi, Taoyuan 335, Taiwan, R.O.C.
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Kao Chin-Hsing
Department of Applied Physics, Chung-Cheng Institute of Technology, National Defense University, Tahsi, Taoyuan 335, Taiwan, R.O.C.
著作論文
- Deposition-Temperature Effect on Nitride Trapping Layer of Silicon–Oxide–Nitride–Oxide–Silicon Memory
- Retention Reliability Improvement of Silicon–Oxide–Nitride–Oxide–Silicon Nonvolatile Memory with N2O Oxidation Tunnel Oxide