Empirical Quantitative Modeling of Threshold Voltage of Sub-50-nm Double-Gate Silicon-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistor

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概要

• 論文の詳細を見る

• We simulated the threhold voltage characteristics of an ultrathin double-gate (DG) silicon-on-insulator metal–oxide–semiconductor field-effect transistor (SOI MOSFET) using the hydrodynamic transport model. It has been shown that threshold voltage increases as SOI layer thickness is reduced in many cases, which is not due to a distinct quantum effect. This stems from an increase in surface potential at the threshold; this increase in surface potential is a physically inevitable result because a reduction in SOI layer thickness decreases inversion layer carrier density per unit area. We proposed models of threshold voltage and surface potential at the threshold, and their availabilities were confirmed by comparing what with the detailed simulation results. We also addressed the short-channel effect on surface potential and proposed a model of drain-induced barrier lowering.

• Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
• 2006-04-30

著者

• Omura Yasuhisa

  Graduate School Of Eng Kansai University

• Omura Yasuhisa

  Graduate School of Engineering, Kansai University, 3-3-35 Yamate-cho, Suita, Osaka 564-8680, Japan

• Tahara Yuki

  Graduate School of Engineering, Kansai University, 3-3-35 Yamate-cho, Suita, Osaka 564-8680, Japan

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• Empirical Quantitative Modeling of Threshold Voltage of Sub-50-nm Double-Gate Silicon-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistor

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