Fabrication of SrTiO3 Field Effect Transistors with SrTiO3-δ Source and Drain Electrodes
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概要
- 論文の詳細を見る
We have developed a process for fabricating top-gate SrTiO3 field-effect transistors (FETs) where the critical channel interface is constructed before forming the source and drain electrodes in order to reduce the density of defects in the transistor channel. Metallic source and drain electrodes are formed by Argon ion milling, which is an efficient way of introducing oxygen vacancies into a thin surface layer of SrTiO3. These vacancies function as donors, inducing metallic conductivity in the electrode regions. This technique can be used to obtain clean interfaces, suppress the formation of lattice imperfections, and avoid impurities in the FET channel because the electronically active interface is constructed at an early step of the device fabrication process. Metallic conductivity of the SrTiO3-δ source and drain electrodes was maintained even after annealing the device at up to 600 °C. Contact with the transistor channel remained ohmic at least down to 50 K.
- Japan Society of Applied Physicsの論文
- 2007-06-25
著者
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Shibuya Keisuke
Institute For Solid State Physics University Of Tokyo
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Ohnishi Tsuyoshi
Institute for Solid State Physics, University of Tokyo, 5-1-5 Kashiwanoha, Kashiwa, Chiba 277-8581, Japan
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LIPPMAA Mikk
Institute for Solid State Physics, University of Tokyo
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Sato Taisuke
Institute for Solid State Physics, University of Tokyo, 5-1-5 Kashiwanoha, Kashiwa, Chiba 277-8581, Japan
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Nishio Kazunori
Institute for Solid State Physics, University of Tokyo, 5-1-5 Kashiwanoha, Kashiwa, Chiba 277-8581, Japan
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OHNISHI Tsuyoshi
Institute for Solid State Physics, The University of Tokyo
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LIPPMAA Mikk
Institute for Solid State Physics, The University of Tokyo
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