An Instruction Mapping Scheme for FU Array Accelerator
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概要
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Recently, we have proposed using a Linear Array Pipeline Processor (LAPP) to improve energy efficiency for various workloads such as image processing and to maintain programmability by working on VLIW codes. In this paper, we proposed an instruction mapping scheme for LAPP to fully exploit the array execution of functional units (FUs) and bypass networks by a mapper to fit the VLIW codes onto the FUs. The mapping can be finished within multi-cycles during a data prefetch before the array execution of FUs. According to an HDL based implementation, the hardware required for mapping scheme is 84% of the cost introduced by a baseline method. In addition, the proposed mapper can further help to shrink the size of array stage, as our results show that their combination becomes 88% of the baseline model in area.
著者
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YAO Jun
Graduate School of Informatics, Kyoto University
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SHIMADA Hajime
Graduate School of Informatics, Kyoto University
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Yao Jun
Graduate School Of Informatics Kyoto Univ.
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YOSHIMURA Kazuhiro
Graduate School of Information Science, Nara Institute of Science and Technology
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IWAKAMI Takuya
Graduate School of Information Science, Nara Institute of Science and Technology
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NAKADA Takashi
Graduate School of Information Science, Nara Institute of Science and Technology
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NAKASHIMA Yasuhiko
Graduate School of Information Science, Nara Institute of Science and Technology
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Shimada Hajime
Graduate School Of Informatics Kyoto University
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Nakashima Yasuhiko
Graduate School Of Information Science Naist
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