CMOS/スピントロニクス融合技術による不揮発性ロジックシステムの展望(ヘッド,スピントロニクス,一般)

概要

論文の詳細を見る
In this article an overview of and an outlook for nonvolatile logic systems based on CMOS/spintronics hybrid technology are described from the viewpoint of energy reduction for CMOS logic systems. Nonvolatile logic systems that are CMOS logic systems with nonvolatile storage/latch circuits are promising for a new type of power-gating architecture, i.e., nonvolatile power-gating (NVPG) that enables them to dramatically reduce the static power. The technologies, advantages, and issues for the NVPG logic systems are reviewed. The concept of break-even time (BET), which is an important performance index to reduce energy consumption in nonvolatile logic systems by executing power-gating, is also discussed, in which we emphasize that "nonvolatile" will not necessarily be "low power" and that low power is only achieved when BET is adequately controlled. Nonvolatile SRAM (NV-SRAM) and nonvolatile flip-flop (NV-FF) are key circuitries to realize NVPG logic systems, and these are simply configured with pseudo-spin-MOSFETs that are circuits for reproducing the functions of spin-transistors using an ordinary MOSFET and a magnetic tunnel junction. An NVPG multicore microprocessor and an NVPG FPGA employing NV-SRAM and NV-FF circuitries are also discussed, which are expected to provide a new development path for future low-power CMOS integrated electronics.
2011-10-06