2305 半導体製造歩留り予測の演算高速化に関する研究(OS2-3 生産管理・プロセス最適化)

概要

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With the higher density of semiconductor devices, the yield prediction simulations such as the CAA (Critical Area Analysis) generally have to take a few days. Therefore, faster calculation is needed to reduce the elapsed time of the prediction. This study aims to propose a management structure of the design layout data which enable the elapsed time of CAA simulation to be considerably faster than the current one while still keeping the simulation accuracy unchanged. A management structure of the layout data using the range tree and interval tree and a prediction method of the query range size were developed to make the 2-dimensional range query in the CAA faster. The CAA calculation which is 10 times to 500 times faster than the current one was achieved.
2008-07-03